Multiprocessor systems employ two or more computer processors that can communicate with each other, such as over a bus or a general interconnect network. In such systems, each processor may have its own memory cache (or cache store) that is separate from the main system memory that the individual processors can access. Cache memory connected to each processor of the computer system can often enable faster access to data than if accessed from the main system memory. Caches are useful because they tend to reduce latency associated with accessing data on cache hits, and they work to reduce the number of requests to system memory. In particular, a write-back cache enables a processor to write changes to data in the cache without simultaneously updating the contents of memory. Modified data can be written back to memory at a later time.
Another technique for reducing processor latency times is pre-fetching. Pre-fetching is the providing of data, such as processor instructions, from a first memory location (e.g., main memory) to a second, more accessible memory location (e.g., a dedicated pre-fetch buffer) before the information is required by the processor. The pre-fetch buffer “anticipates” the data that will be required by the processor, retrieving data according to a pre-fetching algorithm. Proper selection of the pre-fetched data can significantly reduce the access time of the processor for the required data.
Coherency protocols have been developed to ensure that whenever a processor reads or writes to a memory location it receives the correct or true data. Additionally, coherency protocols help ensure that the system state remains deterministic by providing rules to enable only one processor to modify any part of the data at any one time. If proper coherency protocols are not implemented, however, inconsistent copies of data can be generated.